Default config for PIC18F4550 20 Mhz (48 Mhz)

#define FOSC 48000000 
 
code char at __CONFIG1L config1l = 0xff & _PLLDIV_DIVIDE_BY_5__20MHZ_INPUT__1L & _CPUDIV__OSC1_OSC2_SRC___1__96MHZ_PLL_SRC___2__1L & _USBPLL_CLOCK_SRC_FROM_96MHZ_PLL_2_1L;
code char at __CONFIG1H config1h = 0xff & _OSC_HS__HS_PLL__USB_HS_1H & _FCMEN_OFF_1H & _IESO_OFF_1H;
code char at __CONFIG2L config2l = 0xff & _PUT_ON_2L & _BODEN_ON_2L & _BODENV_2_0V_2L & _VREGEN_ON_2L;
code char at __CONFIG2H config2h = 0xff & _WDT_DISABLED_CONTROLLED_2H & _WDTPS_1_32768_2H;
code char at __CONFIG3H config3h = 0xff & _CCP2MUX_RC1_3H & _PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET_3H & _LPT1OSC_ON_3H & _MCLRE_MCLR_ON_RE3_OFF_3H;
code char at __CONFIG4L config4l = 0xff & _STVR_OFF_4L & _LVP_OFF_4L & _ENICPORT_OFF_4L & _ENHCPU_OFF_4L & _BACKBUG_OFF_4L;
code char at __CONFIG5L config5l = 0xff & _CP_0_OFF_5L & _CP_1_OFF_5L & _CP_2_OFF_5L & _CP_3_OFF_5L;
code char at __CONFIG5H config5h = 0xff & _CPB_OFF_5H;
code char at __CONFIG6L config6l = 0xff & _WRT_0_OFF_6L & _WRT_1_OFF_6L & _WRT_2_OFF_6L & _WRT_3_OFF_6L;
code char at __CONFIG6H config6h = 0xff & _WRTB_OFF_6H & _WRTC_OFF_6H & _WRTD_OFF_6H;
code char at __CONFIG7L config7l = 0xff & _EBTR_0_OFF_7L & _EBTR_1_OFF_7L & _EBTR_2_OFF_7L & _EBTR_3_OFF_7L;
code char at __CONFIG7H config7h = 0xff & _EBTRB_OFF_7H;